View CY7C1475V25-100BGXI_3058693.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

72-mbit (2m x 36/4m x 18/1m x 72) flow-through sram with nobl? architecture cy7c1471v25 cy7c1473v25 cy7c1475v25 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05287 rev. *i revised july 04, 2007 features ? no bus latency? (nobl?) architecture eliminates dead cycles between write and read cycles ? supports up to 133 mhz bus operations with zero wait states ? data is transferred on every clock ? pin compatible and functionally equivalent to zbt? devices ? internally self timed output bu ffer control to eliminate the need to use oe ? registered inputs for flow through operation ? byte write capability ? 2.5v/1.8v io supply (v ddq ) ? fast clock-to-output times ? 6.5 ns (for 133-mhz device) ? clock enable (cen ) pin to enable clock and suspend operation ? synchronous self timed writes ? asynchronous output enable (oe ) ? cy7c1471v25, cy7c1473v25 available in jedec-standard pb-free 100-pin tqfp, pb-free and non-pb-free 165-ball fbga package. cy7c1475v25 available in pb-free and non-pb-free 209-ball fbga package. ? three chip enables (ce 1 , ce 2 , ce 3 ) for simple depth expansion. ? automatic power down feature available using zz mode or ce deselect. ? ieee 1149.1 jtag bou ndary scan compatible ? burst capability - linear or interleaved burst order ? low standby power functional description [1] the cy7c1471v25, cy7c1473v25, and cy7c1475v25 are 2.5v, 2m x 36/4m x 18/1m x 72 synchronous flow through burst srams designed specifically to support unlimited true back-to-back read or write operations without the insertion of wait states. the cy7c1471v25, cy7c1473v25, and cy7c1475v25 are equipped with the advanced no bus latency (nobl) logic required to enable consecutive read or write operations with data transferred on every clock cycle. this feature dramatically improves the throughput of data through the sram, especially in systems that r equire frequent write-read transitions. all synchronous inputs pass through input registers controlled by the rising edge of the clock. the clock input is qualified by the clock enable (cen ) signal, which when deasserted suspends operation and extends the previous clock cycle. maximum access delay from the clock rise is 6.5 ns (133-mhz device). write operations are controlled by two or four byte write select (bw x ) and a write enable (we ) input. all writes are conducted with on-chip synchronous self timed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide easy bank selection and output tri-state cont rol. to avoid bus contention, the output drivers are synchrono usly tri-stated during the data portion of a write sequence. selection guide 133 mhz 100 mhz unit maximum access time 6.5 8.5 ns maximum operating current 305 275 ma maximum cmos standby current 120 120 ma note 1. for best practice recommendations, refer to the cypress application note an1064, sram system guidelines .
cy7c1471v25 cy7c1473v25 cy7c1475v25 document #: 38-05287 rev. *i page 2 of 32 logic block diagram ? cy7c1471v25 (2m x 36) logic block diagram ? cy7c1473v25 (4m x 18) c mode bw a bw b we ce1 ce2 ce3 oe read logic dqs dqp a dqp b dqp c dqp d memory array e input register bw c bw d address register write registry and data coherency control logic burst logic a0' a1' d1 d0 q1 q0 a0 a1 adv/ld ce adv/ld c clk cen write drivers d a t a s t e e r i n g s e n s e a m p s write address register a0, a1, a o u t p u t b u f f e r s e zz sleep control c mode bw a bw b we ce1 ce2 ce3 oe read logic dqs dqp a dqp b memory array e input register address register write registry and data coherency control logic burst logic a0' a1' d1 d0 q1 q0 a0 a1 adv/ld ce adv/ld c clk c en write drivers d a t a s t e e r i n g s e n s e a m p s write address register a0, a1, a o u t p u t b u f f e r s e zz sleep control
cy7c1471v25 cy7c1473v25 cy7c1475v25 document #: 38-05287 rev. *i page 3 of 32 logic block diagram ? cy7c1475v25 (1m x 72) a0, a1, a c mode ce1 ce2 ce3 oe read logic dq s dq pa dq pb dq pc dq pd dq pe dq pf dq pg dq ph d a t a s t e e r i n g o u t p u t b u f f e r s memory array e e input register 0 address register 0 write address register 1 burst logic a0' a1' d1 d0 q1 q0 a0 a1 c adv/ld adv/ld e input register 1 s e n s e a m p s o u t p u t r e g i s t e r s e clk cen write drivers bw a bw b we zz bw c bw d bw e bw f bw g bw h sleep control write address register 2 write registry and data coherency control logic
cy7c1471v25 cy7c1473v25 cy7c1475v25 document #: 38-05287 rev. *i page 4 of 32 pin configurations 100-pin tqfp pinout a a a a a1 a0 nc/288m nc/144m v ss v dd a a a a a a dqp b dq b dq b v ddq v ss dq b dq b dq b dq b v ss v ddq dq b dq b v ss nc v dd dq a dq a v ddq v ss dq a dq a dq a dq a v ss v ddq dq a dq a dqp a dqp c dq c dq c v ddq v ss dq c dq c dq c dq c v ss v ddq dq c dq c nc v dd nc v ss dq d dq d v ddq v ss dq d dq d dq d dq d v ss v ddq dq d dq d dqp d a a ce 1 ce 2 bw d bw c bw b bw a ce 3 v dd v ss clk we cen oe a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a adv/ld zz mode a cy7c1471v25 byte a byte b byte d byte c a a
cy7c1471v25 cy7c1473v25 cy7c1475v25 document #: 38-05287 rev. *i page 5 of 32 pin configurations (continued) 100-pin tqfp pinout a a a a a1 a0 nc/288m nc/144m v ss v dd a a a a a a a nc nc v ddq v ss nc dqp a dq a dq a v ss v ddq dq a dq a v ss nc v dd dq a dq a v ddq v ss dq a dq a nc nc v ss v ddq nc nc nc nc nc nc v ddq v ss nc nc dq b dq b v ss v ddq dq b dq b nc v dd nc v ss dq b dq b v ddq v ss dq b dq b dqp b nc v ss v ddq nc nc nc a a ce 1 ce 2 nc nc bw b bw a ce 3 v dd v ss clk we cen oe a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a adv/ld zz mode a cy7c1473v25 byte a byte b a a
cy7c1471v25 cy7c1473v25 cy7c1475v25 document #: 38-05287 rev. *i page 6 of 32 pin configurations (continued) 165-ball fbga (15 x 17 x 1.4 mm) pinout cy7c1471v25 (2m x 36) 234 567 1 a b c d e f g h j k l m n p r tdo nc/576m nc/1g dqp c dq c dqp d nc dq d ce 1 bw b ce 3 bw c cen a ce2 dq c dq d dq d mode nc dq c dq c dq d dq d dq d a v ddq bw d bw a clk we v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck v ss tdi a a dq c v ss dq c v ss dq c dq c nc v ss v ss v ss v ss nc v ss a1 dq d dq d nc/144m nc v ddq v ss tms 891011 nc/288m a a adv/ld nc oe a nc v ss v ddq nc dqp b v ddq v dd dq b dq b dq b nc dq b nc dq a dq a v dd v ddq v dd v ddq dq b v dd nc v dd dq a v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq dq a v ddq a a v ss a a a dq b dq b dq b zz dq a dq a dqp a dq a a v ddq a a0 a v ss nc cy7c1473v25 (4m x 18) 234 567 1 a b c d e f g h j k l m n p r tdo nc/576m nc/1g nc nc dqp b nc dq b ce 1 nc ce 3 bw b cen a ce2 nc dq b dq b mode nc dq b dq b nc nc nc a v ddq nc bw a clk we v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck v ss tdi a a dq b v ss nc v ss dq b nc nc v ss v ss v ss v ss nc v ss a1 dq b nc nc/144m nc v ddq v ss tms 891011 nc/288m a a adv/ld a oe a nc v ss v ddq nc dqp a v ddq v dd nc dq a dq a nc nc nc dq a nc v dd v ddq v dd v ddq dq a v dd nc v dd nc v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq nc v ddq a a v ss a a a dq a nc nc zz dq a nc nc dq a a v ddq a a0 a v ss nc a a a a
cy7c1471v25 cy7c1473v25 cy7c1475v25 document #: 38-05287 rev. *i page 7 of 32 pin configurations (continued) a b c d e f g h j k l m n p r t u v w 1 2 34 5 6 78 9 11 10 dqg dqg dqg dqg dqg dqg dqg dqg dqc dqc dqc dqc nc dqpg dqh dqh dqh dqh dqd dqd dqd dqd dqpd dqpc dqc dqc dqc dqc nc dqh dqh dqh dqh dqph dqd dqd dqd dqd dqb dqb dqb dqb dqb dqb dqb dqb dqf dqf dqf dqf nc dqpf dqa dqa dqa dqa dqe dqe dqe dqe dqpa dqpb dqf dqf dqf dqf nc dqa dqa dqa dqa dqpe dqe dqe dqe dqe aa a a nc nc nc/144m a a nc/288m a aa aa a a1 a0 a aa aa a nc/576m nc nc nc nc nc bws b bws f bws e bws a bws c bws g bws d bws h tms tdi tdo tck nc nc mode nc cen v ss nc clk nc v ss v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v ss v ss v ss v ss v ss v ss v ss v ss nc/1g v dd nc oe ce 3 ce 1 ce 2 adv/ld we v ss v ss v ss v ss v ss v ss v ss zz v ss v ss v ss v ss nc v ddq v ss v ss nc v ss v ss v ss v ss v ss v ss nc v ss v ddq v ddq v ddq v ddq v ddq nc v ddq v ddq v ddq v ddq nc v ddq v ddq v ddq v ddq nc v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq cy7c1475v25 (1m 72) 209-ball fbga (14 x 22 x 1.76 mm) pinout
cy7c1471v25 cy7c1473v25 cy7c1475v25 document #: 38-05287 rev. *i page 8 of 32 pin definitions name io description a 0 , a 1 , a input- synchronous address inputs used to select one of the address locations . sampled at the rising edge of the clk. a [1:0] are fed to the two-bit burst counter. bw a , bw b , bw c , bw d , bw e , bw f , bw g , bw h input- synchronous byte write inputs, active low. qualified with we to conduct writes to the sram. sampled on the rising edge of clk. we input- synchronous write enable input, active low . sampled on the rising edge of clk if cen is active low. this signal must be asserted low to initiate a write sequence. adv/ld input- synchronous advance/load input . used to advance the on-chip addr ess counter or load a new address. when high (and cen is asserted low) the internal burst counter is advanced. when low, a new address can be loaded into the device for an access. after being deselected, adv/ld must be driven low to load a new address. clk input- clock clock input . captures all synchronous inputs to the device. clk is qualified with cen . clk is only recognized if cen is active low. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select or deselect the device. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select or deselect the device. ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select or dese lect the device. oe input- asynchronous output enable, asynchronous input, active low . combined with the synchronous logic block inside the device to control the directio n of the io pins. when low, the io pins are enabled to behave as outputs. when deasserted high, io pins are tri-stated, and act as input data pins. oe is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state, when the device has been deselected. cen input- synchronous clock enable input, active low . when asserted low the clock signal is recognized by the sram. when deasserted high the clock signal is masked. because deasserting cen does not deselect the device, cen can be used to extend the pr evious cycle when required. zz input- asynchronous zz ?sleep? input . this active high input places the device in a non-time-critical ?sleep? condition with data integrity preserved. for normal operation, this pin has to be low or left floating. zz pin has an internal pull down. dq s io- synchronous bidirectional data io lines . as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as out puts, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. the direction of the pins is controlled by oe . when oe is asserted low, the pins behave as outputs. when high, dq s and dqp x are placed in a tri-state condition.the outputs are automatically tri-st ated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of oe . dqp x io- synchronous bidirectional data parity io lines. functionally, these signals are identical to dq s . during write sequences, dqp x is controlled by bw x correspondingly. mode input strap pin mode input. selects the burst order of the device. when tied to gnd selects linear burst sequence. when tied to v dd or left floating selects interleaved burst sequence. v dd power supply power supply inputs to the core of the device . v ddq io power supply power supply for the io circuitry . v ss ground ground for the device . tdo jtag serial output synchronous serial data-out to the jtag circuit . delivers data on the ne gative edge of tck. if the jtag feature is not used, this pin must be le ft unconnected. this pin is not available on tqfp packages.
cy7c1471v25 cy7c1473v25 cy7c1475v25 document #: 38-05287 rev. *i page 9 of 32 functional overview the cy7c1471v25, cy7c1473v25, and cy7c1475v25 are synchronous flow through burst srams designed specifically to eliminate wait states during write-read transitions. all synchronous inputs pass through input registers controlled by the rising edge of the clock. the clock signal is qualified with the clock enable input signal (cen ). if cen is high, the clock signal is not recognized and all internal states are maintained. all synchronous operations are qualified with cen . maximum access delay from the clock rise (t cdv ) is 6.5 ns (133-mhz device). accesses are initiated by asserting all three chip enables (ce 1 , ce 2 , ce 3 ) active at the rising edge of the clock. if cen is active low and adv/ld is asserted low, the address presented to the device is latched. the access can either be a read or write operation, dependi ng on the status of the write enable (we ). byte write select (bw x ) can be used to conduct byte write operations. write operations are qualified by the we . all writes are simplified with on-chip synchronous self timed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) simplify depth expansion. all operations (reads, writes, and deselects) are pipelined. adv/ld must be driven low after the device is deselected to load a new address for the next operation. single read accesses a read access is initiated when the following conditions are satisfied at clo ck rise: (1) cen is asserted low, (2) ce 1 , ce 2 , and ce 3 are all asserted active, (3) we is deasserted high, and (4) adv/ld is asserted low. the address presented to the address inputs is latched into the address register and presented to the memory array and control logic. the control logic determines that a read access is in progress and allows the requested data to propagate to the output buffers. the data is available within 6.5 ns (133-mhz device) provided oe is active low. after the first clock of the read access, the output buffers are controlled by oe and the internal control logic. oe must be driven low to drive out the requested data. on the subsequent clock, another opera tion (read/write/deselect) can be initiated. when the sram is deselected at clock rise by one of the chip enable signals, the output is tri-stated immediately. burst read accesses the cy7c1471v25, cy7c1473v25, and cy7c1475v25 has an on-chip burst counter that enables the user the ability to supply a single address and conduct up to four reads without reasserting the address inputs. adv/ld must be driven low to load a new address into the sram, as described in the single read access section. the sequence of the burst counter is determined by the mode input signal. a low input on mode selects a linear burst mode, a high selects an inter- leaved burst sequence. both burst counters use a0 and a1 in the burst sequence, and wrap s around when incremented sufficiently. a high input on adv/ld increments the internal burst counter regardless of the state of chip enable inputs or we . we is latched at the beginning of a burst cycle. therefore, the type of access (read or write) is maintained throughout the burst sequence. single write accesses write accesses are initiated when these conditions are satisfied at clock rise: ?cen is asserted low ?ce 1 , ce 2 , and ce 3 are all asserted active ?we is asserted low. the address presented to the address bus is loaded into the address register. the write signals are latched into the control logic block. the data li nes are automatically tri-stated regardless of the state of the oe input signal. this allows the external logic to present the data on dqs and dqp x . on the next clock rise the data presented to dqs and dqp x (or a subset for byte write operations, see ?truth table for read/write? on page 12 for details) inputs is latched into the device and the write is complete. additional accesses (read/write/desel ect) can be initiated on this cycle. the data written during the wr ite operation is controlled by bw x signals. the cy7c1471v25, cy7c1473v25, and cy7c1475v25 provide byte writ e capability that is described in the ?truth table for read/write? on page 12 . the input we with the selected bw x input selectively writes to only the desired bytes. bytes not selected during a byte write operation remain unaltered. a synchronous self timed write mechanism is provided to simp lify the write operations. byte write capability is included to greatly simplify read/modify/write sequences, which can be reduced to simple byte write operations. tdi jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. if the jtag feature is not used, this pin can be le ft floating or connected to v dd through a pull up resistor. this pin is not available on tqfp packages. tms jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. if the jtag feature is not used, this pin can be disconnected or connected to v dd . this pin is not available on tqfp packages. tck jtag-clock clock input to the jtag circuitry . if the jtag feature is not used, this pin must be connected to v ss . this pin is not available on tqfp packages. nc - no connects . not internally connected to the die. 144m, 288m, 576m, and 1g are address expansion pins and are not internally connected to the die. pin definitions (continued) name io description
cy7c1471v25 cy7c1473v25 cy7c1475v25 document #: 38-05287 rev. *i page 10 of 32 because the cy7c1471v 25, cy7c1473v25, and cy7c1475v25 are common io devices, data must not be driven into the device while the outputs are active. the oe can be deasserted high before pr esenting data to the dqs and dqp x inputs. this tri-states the output drivers. as a safety precaution, dqs and dqp x are automatically tri-stated during the data portion of a write cycle, regardless of the state of oe . burst write accesses the cy7c1471v25, cy7c1473v25, and cy7c1475v25 have an on-chip burst counter t hat enables the user to supply a single address and conduct up to four write operations without reasserting th e address inputs. adv/ld must be driven low to load the initial address, as described in the single write access section. when adv/ld is driven high on the subsequent clock rise, the chip enables (ce 1 , ce 2 , and ce 3 ) and we inputs are ignored and the burst counter is incre- mented. the correct bw x inputs must be driven in each cycle of the burst write, to write the correct bytes of data. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, da ta integrity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected before entering the ?sleep? mode. ce 1 , ce 2 , and ce 3 , must remain inactive for the duration of t zzrec after the zz input returns low. interleaved burst address table (mode = floating or v dd ) first address a1: a0 second address a1: a0 third address a1: a0 fourth address a1: a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address a1: a0 second address a1: a0 third address a1: a0 fourth address a1: a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min max unit i ddzz sleep mode standby current zz > v dd ? 0.2v 120 ma t zzs device operation to zz zz > v dd ? 0.2v 2t cyc ns t zzrec zz recovery time zz < 0.2v 2t cyc ns t zzi zz active to sleep current t his parameter is sampled 2t cyc ns t rzzi zz inactive to exit sleep current this parameter is sampled 0 ns
cy7c1471v25 cy7c1473v25 cy7c1475v25 document #: 38-05287 rev. *i page 11 of 32 truth table the truth table for cy7c1471v25, cy7c1473v25, and cy7c1475v25 follows. [2, 3, 4, 5, 6, 7, 8] operation address used ce 1 ce 2 ce 3 zz adv/ld we bw x oe cen clk dq deselect cycle none h x x l l x x x l l->h tri-state deselect cycle none x x h l l x x x l l->h tri-state deselect cycle none x l x l l x x x l l->h tri-state continue deselect cycle none x x x l h x x x l l->h tri-state read cycle (begin burst) external l h l l l h x l l l->h data out (q) read cycle (continue burst) next x x x l h x x l l l->h data out (q) nop/dummy read (begin burst) external l h l l l h x h l l->h tri-state dummy read (continue burst) next x x x l h x x h l l->h tri-state write cycle (begin burst) external l h l l l l l x l l->h data in (d) write cycle (continue burst) next x x x l h x l x l l->h data in (d) nop/write abort (begin burst) none l h l l l l h x l l->h tri-state write abort (continue burst) next x x x l h x h x l l->h tri-state ignore clock edge (stall) current x x x l x x x x h l->h - sleep mode none x x x h x x x x x x tri-state notes 2. x = ?don't care.? h = logic high, l = logic low. bw x = l signifies at least one byte write select is active, bw x = valid signifies that the desired byte write selects are asserted, see ?truth table for read/write? on page 12 for details. 3. write is defined by bw x , and we . see ?truth table for read/write? on page 12 . 4. when a write cycle is detected, all io s are tri-stated, even during byte writes. 5. the dqs and dqp x pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 6. cen = h, inserts wait states. 7. device powers up deselected with the ios in a tri-state condition, regardless of oe . 8. oe is asynchronous and is not sampled with the clock rise. it is masked internally during writ e cycles. during a read cycle dqs a nd dqp x = tri-state when oe is inactive or when the devi ce is deselected, and dqs and dqp x = data when oe is active.
cy7c1471v25 cy7c1473v25 cy7c1475v25 document #: 38-05287 rev. *i page 12 of 32 truth table for read/write the read-write truth table for cy7c1471v25 follows. [2, 3, 9] function we bw a bw b bw c bw d read h x x x x write no bytes written lhhhh write byte a ? (dq a and dqp a ) l lhhh write byte b ? (dq b and dqp b )lhlhh write byte c ? (dq c and dqp c )lhhlh write byte d ? (dq d and dqp d ) lhhhl write all bytes l l l l l truth table for read/write the read-write truth table for cy7c1473v25 follows. [2, 3, 9] function we bw b bw a read h x x write ? no bytes written l h h write byte a ? (dq a and dqp a )lhl write byte b ? (dq b and dqp b )llh write both bytes l l l truth table for read/write the read-write truth table for cy7c1475v25 follows. [2, 3, 9] function we bw x read hx write ? no bytes written l h write byte x ? (dq x and dqp x) ll write all bytes l all bw = l note 9. table lists only a partial listing of the byte write combinations. any combination of bw x is valid. appropriate write is bas ed on which byte write is active.
cy7c1471v25 cy7c1473v25 cy7c1475v25 document #: 38-05287 rev. *i page 13 of 32 ieee 1149.1 serial boundary scan (jtag) the cy7c1471v25, cy7c1473v25, and cy7c1475v25 and incorporate a serial boundary scan test access port (tap). this port operates in accordance with ieee standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. t hese functions from the ieee specification are excluded bec ause their inclusion places an added delay in the critical speed path of the sram. note that the tap controller functions in a manner that does not conflict with the operation of other devic es using 1149.1 fully compliant taps. the tap operates using jedec-standard 2.5v or 1.8v io logic levels. the cy7c1471v25, cy7c1473v25, and cy7c1475v25 contain a tap controller, instruction register, boundary scan register, bypass register, and id register. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are inter- nally pulled up and may be unconnected. they may alternately be connected to v dd through a pull up resistor. tdo must be left unconnected. during power up, the device comes up in a reset state, which does not inte rfere with the operation of the device. the 0/1 next to each state repr esents the value of tms at the rising edge of tck. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this ball unconnected if the tap is not used. the ball is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi ball is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information about loading the instruction register, see the tap controller state diagram . tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most significant bit (msb) of any register. (see tap controller block diagram .) test data-out (tdo) the tdo output ball is used to serially clock data-out from the registers. the output is active depending upon the current state of the tap state machine. the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. (see tap controller state diagram.) performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. during power up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap controller state diagram test-logic reset run-test/ idle select dr-scan select ir-scan capture-dr shift-dr capture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 tap controller block diagram bypass register 0 instruction register 0 1 2 identication register 0 1 2 29 30 31 . . . boundary scan register 0 1 2 . . x . . . selection circuitry tck tms tap controller tdi tdo selection circuitry
cy7c1471v25 cy7c1473v25 cy7c1475v25 document #: 38-05287 rev. *i page 14 of 32 tap registers registers are connected between the tdi and tdo balls and enable data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction register. data is serially loaded into the tdi ball on the rising edge of tck. data is output on the tdo ball on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo balls as shown in the ?tap controller block diagram? on page 13 . during power up, the instruction register is loaded with the idcode instru ction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to enable fault isolation of the board-level serial test data path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo balls. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional balls on the sram. the boundary scan register is lo aded with the contents of the ram io ring when the tap co ntroller is in the capture-dr state and is then placed between the tdi and tdo balls when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instructions can be used to capture the contents of the io ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction regi ster. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in ?identification register defini- tions? on page 17 . tap instruction set overview eight different instructions are possible with the three-bit instruction register. all combinations are listed in ?identification codes? on page 18 . three of these instructions are listed as reserved and must not be used. the other five instructions are described in this section in detail. the tap controller used in this sram is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. the tap controller cannot be used to load address data or control signals into the sram and cannot preload the io buffers. the sram does not implement the 1149.1 commands extest or intest or the preload portion of sample/preload; rather, it performs a capture of the io ring when these instructions are executed. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this stat e, instructions are shifted through the instruction register through the tdi and tdo balls. to execute the instruction afte r it is shifted in, the tap controller needs to be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction which is to be executed whenever the instructi on register is loaded with all 0s. extest is not implemented in this sram tap controller, and therefore this device is not compliant to 1149.1. the tap controller does recognize an all-0 instruction. when an extest instruction is loaded into the instruction register, the sram responds as if a sample/preload instruction has been loaded. there is one difference between the two instructions. un like the sample/preload instruction, extest places the sram outputs in a high-z state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo balls and enables the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register during power up or whenever the tap controller is in a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo balls when the tap controller is in a shift-dr state. it also places all sram outputs into a high-z state. sample/preload sample/preload is a 1149.1 m andatory instruction. the preload portion of this instru ction is not implemented, so the device tap controller is not fully 1149.1 compliant. when the sample/preload instruction is loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. the user must be aware that th e tap controller clock can only operate at a frequency up to 20 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output may undergo a transition. the ta p may then try to capture a
cy7c1471v25 cy7c1473v25 cy7c1475v25 document #: 38-05287 rev. *i page 15 of 32 signal while in transition (metastable state). this does not harm the device, but there is no guarantee as to the value that is captured. repeatable results may not be possible. to guarantee that the boundary scan register captures the correct value of a signal, the sram signal must be stabilized long enough to meet the tap c ontroller?s capture setup plus hold time (t cs plus t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/preload instruction. if th is is an issue, it is still possible to capture all other signals and simply ignore the value of the clk captured in the boundary scan register. after the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo balls. note that since the preload part of the command is not implemented, putting the tap to the update-dr state while performing a sample/preload instruction has the same effect as the pause-dr command. bypass when the bypass instruction is loaded in t he instruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo balls. the advantage of the bypass instructio n is that it shortens the boundary scan path when multiple devices are connected together on a board. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions. tap timing t tl test clock (tck) 123456 test mode select (tms) t th test data-out (tdo) t cyc test data-in (tdi) t tmsh t tmss t tdih t tdis t tdox t tdov dont care undefined
cy7c1471v25 cy7c1473v25 cy7c1475v25 document #: 38-05287 rev. *i page 16 of 32 tap ac switching characteristics over the operating range [10, 11] parameter description min max unit clock t tcyc tck clock cycle time 50 ns t tf tck clock frequency 20 mhz t th tck clock high time 20 ns t tl tck clock low time 20 ns output times t tdov tck clock low to tdo valid 10 ns t tdox tck clock low to tdo invalid 0 ns setup times t tmss tms setup to tck clock rise 5 ns t tdis tdi setup to tck clock rise 5 ns t cs capture setup to tck rise 5 ns hold times t tmsh tms hold after tck clock rise 5 ns t tdih tdi hold after clock rise 5 ns t ch capture hold after clock rise 5 ns notes 10.t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 11.test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns.
cy7c1471v25 cy7c1473v25 cy7c1475v25 document #: 38-05287 rev. *i page 17 of 32 1.8v tap ac test conditions input pulse levels ............... ...................... 0.2v to v ddq ? 0.2 input rise and fall time........... .......................................... 1 ns input timing referenc e levels ...........................................0.9v output reference levels...................................................0.9v test load termination supply volt age...............................0.9v 2.5v tap ac test conditions input pulse levels................................................. v ss to 2.5v input rise and fall time .....................................................1 ns input timing reference levels... ...................................... 1.25v output reference levels .......... ...................................... 1.25v test load termination supply vo ltage ............................ 1.25v 1.8v tap ac output load equivalent tdo 0.9v 20pf z = 50 ? o 50 ? 2.5v tap ac output load equivalent tdo 1.25v 20pf z = 50 ? o 50 ? (0c < t a < +70c; v dd = 2.375 to 2.625 unless otherwise noted) [12] parameter description test conditions min. max. unit v oh1 output high voltage i oh = ?1.0 ma, v ddq = 2.5v 2.0 v v oh2 output high voltage i oh = ?100 a v ddq = 2.5v 2.1 v v ddq = 1.8v 1.6 v v ol1 output low voltage i ol = 1.0 ma v ddq = 2.5v 0.4 v v ol2 output low voltage i ol = 100 a v ddq = 2.5v 0.2 v v ddq = 1.8v 0.2 v v ih input high voltage v ddq = 2.5v 1.7 v dd + 0.3 v v ddq = 1.8v 1.26 v dd + 0.3 v v il input low voltage v ddq = 2.5v ?0.3 0.7 v v ddq = 1.8v ?0.3 0.36 v i x input load current gnd < v in < v ddq ?5 5 a identification register definitions instruction field cy7c1471v25 (2mx36) cy7c1473v25 (4mx18) cy7c1475v25 (1mx72) description revision number (31:29) 000 000 000 describes the version number device depth (28:24) 01011 01011 01011 reserved for internal use architecture/memory type(23:18) 001001 001001 0 01001 defines memory type and architecture bus width/density(17:12) 100100 01010 0 110100 defines width and density cypress jedec id code (11:1) 00000110100 00000110 100 00000110100 allows unique identification of sram vendor id register presence indicator (0) 1 1 1 indicates the presence of an id register note 12. all voltages refer to v ss (gnd).
cy7c1471v25 cy7c1473v25 cy7c1475v25 document #: 38-05287 rev. *i page 18 of 32 scan register sizes register name bit size (x36) bit size (x18) bit size (x72) instruction 3 3 3 bypass 1 1 1 id 32 32 32 boundary scan order ? 165fbga 71 52 - boundary scan order ? 209bga - - 110 identification codes instruction code description extest 000 captures io ring contents. places the boundary scan register between tdi and tdo. forces all sram outputs to high-z state. this instruction is not 1149.1 compliant. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operations. sample z 010 captures io ring contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instru ction is reserved for future use. sample/preload 100 captures io ri ng contents. places the boundary scan register between tdi and tdo. does not affect sram operation. th is instruction does not implement 1149.1 preload function and is ther efore not 1149.1 compliant. reserved 101 do not use: this instru ction is reserved for future use. reserved 110 do not use: this instru ction is reserved for future use. bypass 111 places the bypass register between td i and tdo. this operation does not affect sram operation.
cy7c1471v25 cy7c1473v25 cy7c1475v25 document #: 38-05287 rev. *i page 19 of 32 boundary scan exit order (2m x 36) bit # 165-ball id bit # 165-ball id bit # 165-ball id bit # 165-ball id 1c1 21 r3 41j11 61b7 2 d1 22 p2 42 k10 62 b6 3 e1 23 r4 43 j10 63 a6 4d2 24 p6 44h11 64b5 5e2 25 r6 45g11 65a5 6f1 26 r8 46f11 66a4 7g1 27 p3 47e11 67b4 8 f2 28 p4 48 d10 68 b3 9g2 29 p8 49d11 69a3 10 j1 30 p9 50 c11 70 a2 11 k1 31 p10 51 g10 71 b2 12 l1 32 r9 52 f10 13 j2 33 r10 53 e10 14 m1 34 r11 54 a9 15 n1 35 n11 55 b9 16 k2 36 m11 56 a10 17 l2 37 l11 57 b10 18 m2 38 m10 58 a8 19 r1 39 l10 59 b8 20 r2 40 k11 60 a7 boundary scan exit order (4m x 18) bit # 165-ball id bit # 165-ball id bi t # 165-ball id bit # 165-ball id 1 d2 14 r4 27 l10 40 b10 2e2 15 p6 28k10 41a8 3f2 16 r6 29j10 42b8 4g2 17 r8 30h11 43a7 5j1 18 p3 31g11 44b7 6k1 19 p4 32f11 45b6 7l1 20 p8 33e11 46a6 8m1 21 p9 34d11 47b5 9 n1 22 p10 35 c11 48 a4 10 r1 23 r9 36 a11 49 b3 11 r2 24 r10 37 a9 50 a3 12 r3 25 r11 38 b9 51 a2 13 p2 26 m10 39 a10 52 b2
cy7c1471v25 cy7c1473v25 cy7c1475v25 document #: 38-05287 rev. *i page 20 of 32 boundary scan exit order (1m x 72) bit # 209-ball id bit # 209-ball id bit # 209-ball id bit # 209-ball id 1 a1 29 t1 57 u10 85 b11 2a2 30t2 58t11 86b10 3b1 31u1 59t10 87a11 4b2 32u2 60r11 88a10 5 c1 33 v1 61 r10 89 a7 6c2 34v2 62p11 90a5 7 d1 35 w1 63 p10 91 a9 8d2 36w2 64n11 92u8 9 e1 37 t6 65 n10 93 a6 10 e2 38 v3 66 m11 94 d6 11 f1 39 v4 67 m10 95 k6 12 f2 40 u4 68 l11 96 b6 13 g1 41 w5 69 l10 97 k3 14 g2 42 v6 70 p6 98 a8 15 h1 43 w6 71 j11 99 b4 16 h2 44 v5 72 j10 100 b3 17 j1 45 u5 73 h11 101 c3 18 j2 46 u6 74 h10 102 c4 19 l1 47 w7 75 g11 103 c8 20 l2 48 v7 76 g10 104 c9 21 m1 49 u7 77 f11 105 b9 22 m2 50 v8 78 f10 106 b8 23 n1 51 v9 79 e10 107 a4 24 n2 52 w11 80 e11 108 c6 25 p1 53 w10 81 d11 109 b7 26 p2 54 v11 82 d10 110 a3 27 r2 55 v10 83 c11 28 r1 56 u11 84 c10
cy7c1471v25 cy7c1473v25 cy7c1475v25 document #: 38-05287 rev. *i page 21 of 32 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage on v dd relative to gnd........ ?0.5v to +3.6v supply voltage on v ddq relative to gnd ...... ?0.5v to +v dd dc voltage applied to outputs in tri-state........................................... ?0.5v to v ddq + 0.5v dc input voltage ................................... ?0.5v to v dd + 0.5v current into outputs (low).... ..................................... 20 ma static discharge voltage......... ........... ............ ........... >2001v (mil-std-883, method 3015) latch up current .................................................... >200 ma operating range range ambient temperature v dd v ddq commercial 0c to +70c 2.5v?5%/+5% 1.7v to v dd industrial ?40c to +85c electrical characteristics over the operating range [13, 14] parameter description test conditions min max unit v dd power supply voltage 2.375 2.625 v v ddq io supply voltage for 2.5v io 2.375 v dd v for 1.8v io 1.7 1.9 v v oh output high voltage for 2.5v io, i oh = ?1.0 ma 2.0 v for 1.8v io, i oh = ?100 a1.6v v ol output low voltage for 2.5v io, i ol = 1.0 ma 0.4 v for 1.8v io, i ol = 100 a, 0.2 v v ih input high voltage [13] for 2.5v io 1.7 v dd + 0.3v v for 1.8v io 1.26 v dd + 0.3v v v il input low voltage [13] for 2.5v io ?0.3 0.7 v for 1.8v io ?0.3 0.36 v i x input leakage current except zz and mode gnd v i v ddq ?5 5 a input current of mode input = v ss ?30 a input = v dd 5 a input current of zz input = v ss ?5 a input = v dd 30 a i oz output leakage current gnd v i v ddq, output disabled ?5 5 a i dd v dd operating supply current v dd = max., i out = 0 ma, f = f max = 1/t cyc 6.5 ns cycle, 133 mhz 305 ma 8.5 ns cycle, 100 mhz 275 ma i sb1 automatic ce power down current?ttl inputs v dd = max, device deselected, v in v ih or v in v il f = f max , inputs switching 6.5 ns cycle, 133 mhz 170 ma 8.5 ns cycle, 100 mhz 170 ma i sb2 automatic ce power down current?cmos inputs v dd = max, device deselected, v in 0.3v or v in > v dd ? 0.3v, f = 0, inputs static all speeds 120 ma i sb3 automatic ce power down current?cmos inputs v dd = max, device deselected, or v in 0.3v or v in > v ddq ? 0.3v f = f max , inputs switching 6.5 ns cycle, 133 mhz 170 ma 8.5 ns cycle, 100 mhz 170 ma i sb4 automatic ce power down current?ttl inputs v dd = max, device deselected, v in v dd ? 0.3v or v in 0.3v, f = 0, inputs static all speeds 135 ma notes 13. overshoot: v ih (ac) < v dd +1.5v (pulse width less than t cyc /2). undershoot: v il (ac) > ?2v (pulse width less than t cyc /2). 14. t power-up : assumes a linear ramp from 0v to v dd (min.) within 200 ms. during this time v ih < v dd and v ddq < v dd .
cy7c1471v25 cy7c1473v25 cy7c1475v25 document #: 38-05287 rev. *i page 22 of 32 capacitance tested initially and after any design or proc ess change that may affect these parameters. parameter description test conditions 100 tqfp max. 165 fbga max. 209 fbga max. unit c address address input capacitance t a = 25 c, f = 1 mhz, v dd = 2.5v v ddq = 2.5v 6 6 6 pf c data data input capacitance 5 5 5 pf c ctrl control input capacitance 8 8 8 pf c clk clock input capacitance 6 6 6 pf c io input-output capacitance 5 5 5 pf thermal resistance tested initially and after any design or proc ess change that may affect these parameters. parameter description test conditions 100 tqfp package 165 fbga package 209 fbga package unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, according to eia/jesd51. 24.63 16.3 15.2 c/w jc thermal resistance (junction to case) 2.28 2.1 1.7 c/w ac test loads and waveforms output r = 1667 ? r = 1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v l = 1.25v 2.5v all input pulses v ddq gnd 90% 10% 90% 10% 1 ns 1 ns (c) 2.5v io test load output r = 14 k ? r = 14 k ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v l = 0.9v 1.8v all input pulses v ddq ? 0.2 0.2 90% 10% 90% 10% 1 ns 1 ns (c) 1.8v io test load
cy7c1471v25 cy7c1473v25 cy7c1475v25 document #: 38-05287 rev. *i page 23 of 32 switching characteristics over the operating range. timing reference level is 1.25v when v ddq = 2.5v and is 0.9v when v ddq = 1.8v. test conditions shown in (a) of ?ac test loads and waveforms? on page 22 unless otherwise noted. parameter description 133 mhz 100 mhz unit min max min max t power 11ms clock t cyc clock cycle time 7.5 10 ns t ch clock high 2.5 3.0 ns t cl clock low 2.5 3.0 ns output times t cdv data output valid after clk rise 6.5 8.5 ns t doh data output hold after clk rise 2.5 2.5 ns t clz clock to low-z [16, 17, 18] 3.0 3.0 ns t chz clock to high-z [16, 17, 18] 3.8 4.5 ns t oev oe low to output valid 3.0 3.8 ns t oelz oe low to output low-z [16, 17, 18] 00ns t oehz oe high to output high-z [16, 17, 18] 3.0 4.0 ns setup times t as address setup before clk rise 1.5 1.5 ns t als adv/ld setup before clk rise 1.5 1.5 ns t wes we , bw x setup before clk rise 1.5 1.5 ns t cens cen setup before clk rise 1.5 1.5 ns t ds data input se tup before clk rise 1.5 1.5 ns t ces chip enable setup before clk rise 1.5 1.5 ns hold times t ah address hold after clk rise 0.5 0.5 ns t alh adv/ld hold after clk rise 0.5 0.5 ns t weh we , bw x hold after clk rise 0.5 0.5 ns t cenh cen hold after clk rise 0.5 0.5 ns t dh data input hold after clk rise 0.5 0.5 ns t ceh chip enable hold after clk rise 0.5 0.5 ns notes 15. this part has a voltage regulator internally; t power is the time that the power needs to be supplied above v dd (minimum) initially, before a read or write operation can be initiated. 16. t chz , t clz ,t oelz , and t oehz are specified with ac test conditions shown in part (b) of ?ac test loads and waveforms? on page 22 . transition is measured 200 mv from steady-state voltage. 17. at any supplied voltage and temperature, t oehz is less than t oelz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not impl y a bus contention condition, bu t reflect parameters guaranteed over worst case user conditions. device is designed to achieve high-z before low-z under the same system conditions. 18. this parameter is sampled and not 100% tested.
cy7c1471v25 cy7c1473v25 cy7c1475v25 document #: 38-05287 rev. *i page 24 of 32 switching waveforms figure 1 shows read-write timing waveform. [19, 20, 21] figure 1. read/write timing write d(a1) 123 456789 clk t cyc t cl t ch 10 ce t ceh t ces we cen t cenh t cens bw x adv/ld t ah t as address a1 a2 a3 a4 a5 a6 a7 t dh t ds dq command t clz d(a1) d(a2) q(a4) q(a3) d(a2+1) t doh t chz t cdv write d(a2) burst write d(a2+1) read q(a3) read q(a4) burst read q(a4+1) write d(a5) read q(a6) write d(a7) deselect oe t oev t oelz t oehz dont care undefined d(a5) t doh q(a4+1) d(a7) q(a6) notes 19. for this waveform zz is tied low. 20. when ce is low, ce 1 is low, ce 2 is high, and ce 3 is low. when ce is high, ce 1 is high, ce 2 is low or ce 3 is high. 21. order of the burst sequence is determin ed by the status of the mode (0 = linear, 1 = interleaved). burst operations are opti onal.
cy7c1471v25 cy7c1473v25 cy7c1475v25 document #: 38-05287 rev. *i page 25 of 32 figure 2 shows nop, stall and deselect cycles waveform. [19, 20, 22] figure 2. nop, stall and deselect cycles switching waveforms (continued) read q(a3) 456 78910 a3 a4 a5 d(a4) 123 clk ce we cen bw [a:d] adv/ld address dq command write d(a4) stall write d(a1) read q(a2) stall nop read q(a5) deselect continue deselect dont care undefined t chz a1 a2 q(a2) d(a1) q(a3) t doh q(a5) note 22. the ignore clock edge or sta ll cycle (clock 3) illustrates cen being used to create a pause. a write is not performed during this cycle.
cy7c1471v25 cy7c1473v25 cy7c1475v25 document #: 38-05287 rev. *i page 26 of 32 figure 3 shows zz mode timing waveform. [23, 24] figure 3. zz mode timing switching waveforms (continued) t zz i supply clk zz t zzrec all inputs (except zz) dont care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only notes 23. device must be deselected when entering zz mode. see ?truth table? on page 11 for all possible signal conditions to deselect the device. 24. dqs are in high-z when exiting zz sleep mode.
cy7c1471v25 cy7c1473v25 cy7c1475v25 document #: 38-05287 rev. *i page 27 of 32 ordering information not all of the speed, package and temper ature ranges are available. please cont act your local sales representative or visit www.cypress.com for actual products offered. speed (mhz) ordering code package diagram part and package type operating range 133 cy7c1471v25-133axc 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) pb-free commercial cy7c1473v25-133axc cy7c1471v25-133bzc 51-85165 165-ball fine-p itch ball grid array (15 x 17 x 1.4 mm) cy7c1473v25-133bzc cy7c1471v25-133bzxc 51- 85165 165-ball fine-pit ch ball grid array (15 x 17 x 1.4 mm) pb-free cy7c1473v25-133bzxc cy7c1475v25-133bgc 51-85167 209-ball fine-pit ch ball grid array (14 22 1.76 mm) cy7c1475v25-133bgxc 209-ball fine-pitch ball grid array (14 22 1.76 mm) pb-free cy7c1471v25-133axi 51-85050 100-pin thin quad fl at pack (14 x 20 x 1.4 mm) pb-free lndustrial cy7c1473v25-133axi cy7c1471v25-133bzi 51-85165 165-ball fine-p itch ball grid array (15 x 17 x 1.4 mm) cy7c1473v25-133bzi cy7c1471v25-133bzxi 51- 85165 165-ball fine-pit ch ball grid array (15 x 17 x 1.4 mm) pb-free cy7c1473v25-133bzxi cy7c1475v25-133bgi 51-85167 209-ball fine-pit ch ball grid array (14 22 1.76 mm) cy7c1475v25-133bgxi 209-ball fine-pitch ball grid array (14 22 1.76 mm) pb-free 100 cy7c1471v25-100axc 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) pb-free commercial cy7c1473v25-100axc cy7c1471v25-100bzc 51-85165 165-ball fine-p itch ball grid array (15 x 17 x 1.4 mm) cy7c1473v25-100bzc cy7c1471v25-100bzxc 51- 85165 165-ball fine-pit ch ball grid array (15 x 17 x 1.4 mm) pb-free cy7c1473v25-100bzxc cy7c1475v25-100bgc 51-85167 209-ball fine-pit ch ball grid array (14 22 1.76 mm) cy7c1475v25-100bgxc 209-ball fine-pitch ball grid array (14 22 1.76 mm) pb-free cy7c1471v25-100axi 51-85050 100-pin thin quad fl at pack (14 x 20 x 1.4 mm) pb-free lndustrial cy7c1473v25-100axi cy7c1471v25-100bzi 51-85165 165-ball fine-p itch ball grid array (15 x 17 x 1.4 mm) cy7c1473v25-100bzi cy7c1471v25-100bzxi 51- 85165 165-ball fine-pit ch ball grid array (15 x 17 x 1.4 mm) pb-free cy7c1473v25-100bzxi cy7c1475v25-100bgi 51-85167 209-ball fine-pit ch ball grid array (14 22 1.76 mm) CY7C1475V25-100BGXI 209-ball fine-pitch ball grid array (14 22 1.76 mm) pb-free
cy7c1471v25 cy7c1473v25 cy7c1475v25 document #: 38-05287 rev. *i page 28 of 32 package diagrams figure 4. 100-pin thin plastic quad flatpack (14 x 20 x 1.4 mm), 51-85050 note: 1. jedec std ref ms-026 2. body length dimension does not include mold protrusion/end flash mold protrusion/end flash shall not exceed 0.0098 in (0.25 mm) per side 3. dimensions in millimeters body length dimensions are max plastic body size including mold mismatch 0.300.08 0.65 20.000.10 22.000.20 1.400.05 121 1.60 max. 0.05 min. 0.600.15 0 min. 0.25 0-7 (8x) stand-off r 0.08 min. typ. 0.20 max. 0.15 max. 0.20 max. r 0.08 min. 0.20 max. 14.000.10 16.000.20 0.10 see detail a detail a 1 100 30 0 5 1 3 51 80 81 gauge plane 1.00 ref. 0.20 min. seating plane 51-85050-*b
cy7c1471v25 cy7c1473v25 cy7c1475v25 document #: 38-05287 rev. *i page 29 of 32 figure 5. 165-ball fbga (15 x 17 x 1.4 mm), 51-85165 package diagrams (continued) a 1 pin 1 corner 17.000.10 15.000.10 7.00 1.00 ?0.450.05(165x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.35 1.40 max. seating plane 0.530.05 0.25 c 0.15 c pin 1 corner top view bottom view 2 3 4 5 6 7 8 9 10 10.00 14.00 b c d e f g h j k l m n 11 11 10 9 8 67 5 4 3 2 1 p r p r k m n l j h g f e d c b a c 1.00 5.00 0.36 +0.05 -0.10 51-85165-*a
cy7c1471v25 cy7c1473v25 cy7c1475v25 document #: 38-05287 rev. *i page 30 of 32 ? cypress semiconductor corporation, 2002-2007. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent o r other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. nobl and no bus latency are trademarks of cypress semiconduc tor corporation. zbt is a trademark of integrated device technology, inc. all product and company names mentioned in this document are the trademarks of their respective holders. figure 6. 209-ball fbga (14 x 22 x 1.76 mm), 51-85167 package diagrams (continued) 51-85167-**
cy7c1471v25 cy7c1473v25 cy7c1475v25 document #: 38-05287 rev. *i page 31 of 32 document history page document title: cy7c1471v25/cy7c1473v 25/cy7c1475v25, 72-mbit (2m x 36/4m x 18/1m x 72) flow-through sram with nobl? architecture document number: 38-05287 rev. ecn no. issue date orig. of change description of change ** 114674 08/06/02 pks new data sheet *a 121522 01/27/03 cjm updated f eatures for package offering updated ordering information changed advanced information to preliminary *b 223721 see ecn njy changed timing diagrams changed logic block diagrams modified functional description modified ?functional overview? section added boundary scan order for all packages included thermal numbers and capacitance values for all packages removed 150mhz speed grade offering included isb and idd values changed package outline for 165fbga package and 209-ball bga package removed 119-bga package offering *c 235012 see ecn ryq minor change: the data sheets do not match on the spec system and external web *d 243572 see ecn njy changed ball h2 from v dd to nc in the 165-ball fbga package in page 6 changed ball r11 in 209-ball bga package from dqpa to dqpe in page 7 modified capacitance values on page 21 *e 299511 see ecn syt removed 117-mhz speed bin changed ja from 16.8 to 24.63 c/w and jc from 3.3 to 2.28 c/w for 100 tqfp package on page # 22 added pb-free information for 100-pin tqfp, 165 fbga and 209 bga packages added comment of ?pb-free bg package s availability? below the ordering information *f 323039 see ecn pci address expansion pins/balls in the pinouts for all packages are modified as per jedec standard added address expansion pins in the pin definitions table modified v ol , v oh test conditions changed package name from 209-ball pbga to 209-ball fbga on page# 7 added industrial temperature range added pb-free information in the ordering information table removed comment of ?pb-free bg packa ges availability? below the ordering information updated ordering information table *g 416221 see ecn nxr converted from preliminary to final changed address of cypress semiconductor corporation on page# 1 from ?3901 north first street? to ?198 champion court? changed the description of i x from input load current to input leakage current on page# 20 changed the i x current values of mode on page # 20 from ?5 a and 30 a to ?30 a and 5 a changed the i x current values of zz on page # 20 from ?30 a and 5 a to ?5 a and 30 a changed v ih < v dd to v ih < v dd on page # 20 replaced package name column with package diagram in the ordering information table updated ordering information table
cy7c1471v25 cy7c1473v25 cy7c1475v25 document #: 38-05287 rev. *i page 32 of 32 *h 472335 see ecn vkn corrected the typo in the pin configuration for 209-ball fbga pinout (corrected the ball name for h9 to v ss from v ssq ). added the maximum rating for supply voltage on v ddq relative to gnd. changed t th , t tl from 25 ns to 20 ns and t tdov from 5 ns to 10 ns in tap ac switching characteristics table. updated the ordering information table. *i 1274732 see ecn vkn/aesa corrected typo in the ?nop, stall and deselect cycles? waveform document title: cy7c1471v25/cy7c1473v 25/cy7c1475v25, 72-mbit (2m x 36/4m x 18/1m x 72) flow-through sram with nobl? architecture document number: 38-05287 rev. ecn no. issue date orig. of change description of change

▲Up To Search▲

Price & Availability of CY7C1475V25-100BGXI

	To Download CY7C1475V25-100BGXI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .